1. Field of the Invention
The present invention generally relates to a data management system having two CPUs coupled to each other via a dual-port memory, and more particularly to a data management system in which the two CPUs operate independently and data is transferred between the two CPUs via the dual-port memory.
2. Description of the Prior Art
Recently, it has been required that data management systems handle a large amount of data at high speeds. For example, supervisory devices or control devices provided in data transmission devices in an optical communications system handle a large amount of data at high speeds in order to supervise internal circuits of the data transmission devices and notify a host device of a failure which has occurred in the system. Recently, a data management system having a plurality of CPUs (microcomputers) has been proposed, in which one of the CPUs manages the other CPUs which performs decentralized functions.
In such a data management system, data, such as data necessary to provide the functions (used in processing in the CPUs 1 and 2), is transferred between the CPUs in order to realize various functions of the data management system. If a failure has occurred in one of the CPUs, the other CPUs cannot communicate with the defective CPU. When the failure has been eliminated, the communications with the previously defective CPU are started. At this time, there is a possibility that data handled by the recovered CPU may be inconsistent with data handled by the other CPUs. Hence, it is required that the recovered CPU recovers correct data without affecting the other CPUs and again provide the functions of the data management system by cooperating with the other CPUs.
FIG. 1 is a conventional data management system, which includes two CPUs 1 and 2, a dual-port random access memory (DPRAM) 3, a read only memory (ROM) 4, and an electrically erasable programmable ROM (E.sup.2 PROM) 5. The dual-port RAM 3 is provided between the CPU 1 and the CPU 2. The ROM 4, which is connected to the CPU 1, stores data used to initialize the CPUs 1 and 2. The E.sup.2 PROM 5 provides a backup memory area used to save data.
The CPU 1 and the CPU 2 have respective databases having the same contents. One of the CPUs 1 and 2 executes an operation on data processed by the other CPU. Data is transferred between the CPUs 1 and 2 via the dual-port RAM 3. The CPUs 1 and 2 are initialized on the basis of the data stored in the ROM 4 at the commencement of the operations of the CPUs 1 and 2. While the system is normally operating, data handled in the system is saved in the E.sup.2 PROM 5. When a failure which has occurred in either the CPU 1 or the CPU 2 is eliminated, the backup data saved in the E.sup.2 PROM 5 is used.
For example, the CPU 1 is provided in a host device, and the CPU 2 is provided in a communications device. Data being considered is related to, for example, the supervising of the communications device. More specifically, the data indicates what should be supervised and what results of the supervising should be transferred to the host device.
The CPU 1 unconditionally saves all data in the E.sup.2 PROM 5 for backup. Hence, it takes a long time to write data into the E.sup.2 PROM 5 under the control of the CPU 1. There is a possibility that the CPU 1 is writing data into the E.sup.2 PROM 5 even when the CPU 2 is ready to handle data. Hence, the entire operation of the data management system cannot be performed until the CPU 1 completes the writing of data into the E.sup.2 PROM 5. Even if a failure has been immediately recovered from, the system cannot restart until the completion of writing data into the E.sup.2 PROM 5 under the control of the CPU 1.
If failures which have occurred in the both CPUs 1 and 2 are eliminated, the CPUs 1 and 2 unconditionally restart on the basis of the data stored in the ROM 4. Hence, data handled after the CPUs 1 and 2 restart may be inconsistent with data handled before the failures occurred. In this case, the data management system may malfunction.